The present invention relates to a phase locked loop circuit adapted for use in high speed communication systems. More particularly, the invention concerns a digital phase locked loop circuit especially adapted for synchronizing the frequency of a remote data input signal and an internal feedback signal to provide a reliable reference clock output signal.
Phase locked loop circuits are well known in the prior art, for the purpose of providing data output signals that are continually synchronized with a clock signal. Usually phase locked loop circuits accomplish frequency and phase synchronization by means of comparing the input data signal with a feedback signal and then eliminating the difference in frequency and phase between the two signals by means of incremental adjustments to one of the signals until the comparator records a null output. One such system is described in U.S. Pat. No. 3,777,272, for example.
The above mentioned systems are satisfactory for many purposes. However, such systems have a major shortcoming in that phase adjustment is accomplished in fixed increments by adding or deleting one pulse at a time from the signal to be corrected until a synchronized output condition is reached. Obviously, the addition of one pulse at a time to a signal requires a longer synchronization time than a system wherein the adjustment is provided in multiple pulse steps. Moreover, the systems of the prior art do not always provide satisfactory synchronization when the incoming data signal exhibits transient conditions in addition to steady state phase jitter.
Accordingly, a need exists for a digital phase locked loop circuit which is able to maintain synchronization between an input data signal and a local clock or feedback signal during conditions of both phase jitter and transient interference.